1. Field of the Invention
The present invention relates to a NAND flash memory device and method of reading the same, and more particularly, to a NAND flash memory device capable of reducing leakage currents therein.
2. Discussion of Related Art
A NAND flash memory device is comprised of memory cells serially connected between a drain selection transistor and a source selection transistor in the unit of 16 or 32 in number. A single block is defined as a group of memory cells associated with a cell string sharing the same wordline.
It is general to distinguish the cell blocks into selected cell blocks and deselected cell blocks for a read operation in accordance with conditions of voltages applied to the cell blocks.
First, considering voltage conditions associated with a selected cell block during a read operation, 0V is applied to a selected wordline through an X-decoder, while 4.5V is applied to pass wordlines, the drain selection transistor, and the source selection transistor. 0V is applied to a common source line and a bulk, while 1V is applied to a bitline.
On the other side, considering voltage conditions associated with deselected cell blocks during a read operation, the X-decoder makes all of wordlines, drain selection transistors, and source selection transistors be floated. The source selection transistors are conductive over a selected cell block and deselected cell blocks. A source selection transistor of a deselected cell block may be coupled to 4.5V of voltage. Voltage conditions for a common source line, a bulk and bitlines are identical to those of the selected cell block.
With such voltage conditions, leakage currents arising from drain selection transistors and source selection transistors may cause malfunctions in the NAND flash memory device. Usually, a NAND cell array constructed of units of cell strings basically has a very small ON-current of 200 nA through 400 nA. In order to obtain a short sensing time, it is necessary to control leakage currents to be generated from the deselected cell blocks.
In addition, a NAND flash memory cell is confined to have a leakage current of several pico-Amperes (pA) under the voltage condition of 8V in order to prevent program disturbance due to junction leakage effects. Therefore, it is desired to form a deep junction structure even in the dimension of a memory cell with a gate length 0.1 μm and a selection transistor with a gate length 0.18 μm. Such shrinking-down in morphological configuration in the NAND flash memory device is inevitable to be weak in junction-to-junction leakage, i.e., a punch-through.